A MEMS (Micro Electro Mechanical Systems) device, in which micro electrical components or micro mechanical components are integrated, is known. As the MEMS device, a micro-machine, a pressure sensor, an ultra-small motor etc. is exemplified. A semiconductor device which is produced by stacking LSI (Large Scale Integration) on a semiconductor wafer is known. Such a semiconductor device can reduce such as increase of leakage current and a signal delay in wiring.
A room temperature bonding for bonding wafers by contacting wafer surfaces with each other, which are activated in a vacuum environment, is known. For example, a bonding method of silicon wafers is disclosed in JP Patent No. 2,791,429 (Patent Literature 1). The room temperature bonding method of the silicon wafers is a method of bonding one silicon wafer and another silicon wafer to each other. According to the room temperature bonding method of the silicon wafers, bonding surfaces of both the silicon wafers are sputtered and etched with an inert gas ion beam or an inert gas fast atom beam in a vacuum environment at room temperature, prior to bonding.
In addition, a manufacturing method and a laminated structure are disclosed in JP 2004-358602 A (Patent Literature 2). According to the manufacturing method of the laminated structure, a donor substrate, in which a plurality of cross-section pattern members corresponding to cross-section patterns of the structure is formed, is prepared. Then, the donor substrate and a target substrate are disposed such that these substrates are faced with each other. And then, the target substrate is aligned to the cross-section pattern member and pressed to the cross-section pattern member. After that, these substrates are separated from each other. By repeating the above processing, the cross-section pattern members are transferred to the target substrate and the laminated structure, in which the cross-section patterns are laminated and bonded, is manufactured. Preparation of the donor substrate includes a first step of forming a reverse pattern layer obtained by reversing a cross-sectional pattern of the structure on the donor substrate, a second step of forming a plurality of the cross-section pattern members by plating in space portions corresponding to the cross-sectional pattern of the structure with the reverse pattern layer, and a third step of removing the reverse pattern layer.
Moreover, a room temperature bonding method is disclosed in Japanese Patent No. 4,172,806 (Patent Literature 3: corresponding to US2010/0,000,663A1). This room temperature bonding method is a method of bonding a plurality of substrates via an intermediate material at room temperature. This room temperature bonding method includes a step of forming the intermediate material on a substrate surface to be bonded by sputtering a plurality of targets physically, and a step of activating the substrate surface to be bonded by physical sputtering.
Such room temperature bonding is suitable for manufacturing the MEMS device, and it is suitable for manufacturing the semiconductor device. Therefore, in recent years, MEMS devices and semiconductor devices using the room temperature bonding apparatus has been produced, and the devices using the room temperature bonding are spreading. As a result, regarding room temperature bonding, a request for bonding different kinds of materials to each other is coming out. The different kinds of materials are, for example, different kinds of materials never bonded to each other so far, or different kinds of materials which are difficult to be bonded to each other.
Between different kinds of materials, etching rate or thickness of an oxide film and an adsorption layer is different for each material. Therefore, when etching surfaces of two wafers (substrates), which are composed of different materials from each other, under the same condition (as disclosed in Patent Literature 1), there is a case that the oxide film and the adsorption layer on each wafer surface cannot be appropriately removed and that it is difficult to bond both wafers to each other. For example, there may be a case that an oxide film on a surface of one wafer is removed and an oxide film on a surface of the other wafer is remained. Alternatively, there may be a case that an oxide film on a surface of one wafer is removed while a surface roughness of the wafer is proper and an oxide film on a surface of the other wafer is too much removed while a surface roughness of the wafer is degraded. Both of the cases, it is impossible to bond the both wafers to each other. Note that the adsorption layer is, for example, an adsorption film including contaminants deposited on a bonding target wafer (substrate) which prevent the bonding, or an inert layer such as a layer of natural oxide film to be removed. Moreover, as to different materials, it is treated as different materials, if a surface state is clearly different for each material even if the material itself is the same for each material.
In addition, in a case that forming an intermediate layer aggressively on surfaces (surfaces to be bonded) of two wafers (substrates), which are made of different materials with each other, and that the two wafers are bonded via the intermediate layer as a bonding layer, it is imagined that conditions of etching are the same for each wafer surface when the simultaneous etching of the both wafer surfaces is performed. Therefore, in this case, the oxide film and the adsorption layer on each wafer surface may not be appropriately removed as in the case of using the technic disclosed in the Patent Literature 1. As a result, it is difficult to bond both wafers to each other.